Present trends in dynamic random access memory (DRAM) technology are constantly driven towards reduction in minimum feature size, F, and more compact cell layouts, i.e., denser than 8F.sup.2. As a result of the need for ever increasing array densities, the scalability of contemporary planar metal oxide semiconductor field effect transistor (MOSFET) cells for F=150 nm and smaller dimensions is facing fundamental concerns. The main concern with the scalability of the MOSFET cell is the increased P-well doping concentration needed to meet off-current objectives. It is well known in the art that increased array well doping concentration may result in a marked increase in array junction leakage, which degrades retention time. The problem of scalability related to the MOSFET cell, by itself, is driving the paradigm shift towards vertical MOSFET access transistors in the array.
A great depth of knowledge of, and experience with, deep trench (DT) storage capacitor technology exists. However, with increasingly smaller groundrules and denser cell layouts, the ability to obtain adequate DT storage capacitance (on the order of about 35fF) is being seriously challenged. The difficulty in obtaining adequate DT storage capacitance is due to several factors including: (1) limitations on the scalability of the thickness of the node dielectric; (2) limitations on the etch depth of the DT; and (3) reduction of capacitance area that occurs with groundrule reduction, e.g., scaling, and more dense cell layouts, i.e., 6F.sup.2 and 7F.sup.2 vs. 8F.sup.2. Reactive-ion etching (RIE) lag effect caused by smaller storage trench openings makes etching adequate deep trenches difficult. Filling of these extremely high aspect ratio (&gt;50:1) trenches also presents major difficulties.
Furthermore, the high aspect ratios associated with aggressively scaled DT capacitors result in increased series resistance which, in turn, results in decreased signal development within a given time window. For a 6F.sup.2 cell with a near 1.times.1 DT opening, it is expected that the above mentioned problems of capacitance and resistance may become a major problem by the 120 nm generation. For DRAM producers with firmly established DT capacitor technology as the main stream storage element for longer than the past decade, it would be costly to switch to an alternative storage technology such as stacked capacitors with a high dielectric constant.
Thus, there is a need for DRAM cells containing vertical access transistors, dense layouts (denser than about 8F.sup.2) and trench storage capacitors which yield sufficient capacitance and reduced series resistance to avoid degraded signal development.
Although some existing DRAM cells employing vertical MOSFETs offer very significant scalability advantages over conventional planar designs practiced today, there is still a great deal of room for improvement. For example, for cells using vertical MOSFETs and trench storage capacitors, a single bitline contact is commonly used to access a pair of bits; the pair of bits share a common silicon active area (AA). In this type of cell, dynamic coupling between the two back-to-back vertical MOSFETs results in charge pumping effects and loss of signal. Modeling has shown that electrons pumped into the P-well from a collapsing channel inversion layer of one cell may be collected by the storage node of the adjacent cell sharing the same AA. These coupling effects are accentuated as dimensions are scaled down. Modeling projections indicate that scalability to 100 nm and below may be problematic because of dynamic charge loss due to coupling between adjacent cells.
In addition to charge pumping problems, very dense prior art designs suffer from threshold voltage variations in the size of the silicon AA which occurs with overlay (alignment) errors between various masking levels and with dimensional variations of features formed by these masking levels.
Another problem faced with aggressively scaled DRAM cells is the increased aspect ratio (height to width) of the isolation regions. This is especially a concern with vertical MOSFETs in the array because of the requirement that the isolation trench be deep enough to cut the strap so as to prevent cell-to-cell leakage between straps. Typically, it is required that the isolation trench be at least 500 nm in depth to isolate the straps of the vertical MOSFETs. If the thickness of the pad layer is included, an isolation trench aspect ratio of 7:1 is anticipated by the 100 nm generation.
Prior art memory cell layouts also suffer from the bitline pitch limiting the density of the array. Moreover, in prior art memory cells, a truly planar structure is difficult to obtain; therefore prior art memory cells have decreased depth of focus for the bitline and higher wiring levels.
In view of the drawbacks mentioned hereinabove with prior art DRAM cell designs, there is a continued need to develop new and improved DRAM cell designs that are denser than prior art designs and have a larger DT size. A larger DT size is advantageous in dense DRAM cells since it provides a large storage capacitance and reduced series resistance to the array cell.